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copyright ? cirrus logic, inc. 2005 (all rights reserved) http://www.cirrus.com cs5321/22 24-bit, variable-bandwidth a/d converter chipset features z cmos a/d converter chipset z dynamic range - 130 db @ 25 hz bandwidth - 121 db @ 411 hz bandwidth z delta-sigma architecture - fourth-order modulator - variable oversampling: 64x to 4096x - internal track-and-hold amplifier z cs5321 signal-to-dist ortion: 115 db z clock-jitter-toler ant architecture z input voltage range: + 4.5 v z flexible filter chip - hardware- or software-selectable options - seven selectable filter corners (-3 db) frequencies: 25, 51, 102, 205, 411, 824 and 1650 hz z low power dissipation: <100 mw description the cs5321/cs5322 chipset functions as a unique a/d converter intended for very high-resolution measurement of signals below 1600 hz. it is specif- ically designed for applications that require both a high dynamic range and a low total harmonic distor- tion. the chipset performs sampling, a/d conversion, and anti-alias filtering. the cs5321 uses delta-sigma modulation to pro- duce highly accurate conversions. the ? modulator oversamples, virtually eliminating the need for external analog anti-alias filters. the cs5322 linear-phase fir digital filter decimates the output to any one of seven selectable update peri- ods: 16, 8, 4, 2, 1, 0.5, and 0.25 milliseconds. data is output from the digital filter in a 24-bit serial format. ordering in formation see page 36 . rsel v dd1 ainr ain+ ain- v ss1 agnd analog modulator mdata mclk mflg reset r/w h/s sclk sid sod error drdy orcal deca decb decc cs clkin sync vd+ tdata pwdn useor dgnd vd+ dgnd csel digital filter cs5321 cs5322 v ss2 dgnd v dd2 lpwr ofst mdata hbr msync vref+ vref- sep ?05 ds454f2
cs5321/22 2 ds454f2 table of contents 1. characteristics a nd specifications . ................ ................ .............. 4 cs5321 analog characteristics .................................................... 4 cs5321 switching characteristics .............................................. 6 cs5321 digital characteristics ..................................................... 7 cs5321 recommended operation conditions ........................... 7 cs5321 absolute maximum ratings . ................ ................ .............. 7 cs5322 filter characteristics ...................................................... 8 cs5322 power supply ....................................................................... 10 cs5322 switching characteristics ............................................ 10 cs5322 digital characteristics ................................................... 15 cs5322 recommended operation conditions ......................... 15 cs5322 absolute maximum ratings . ................ ................ ............ 15 2. general description ............................................................................ 16 2.1. analog input ...................................................................................... 18 2.2. the ofst pin.................................................................................... 18 2.3. input range and overrange conditions ............................................ 19 2.4. voltage reference ............................................................................. 20 2.5. clock source ..................................................................................... 20 2.6. low power mode ............................................................................... 21 2.7. digital interface and data form at...................................................... 21 2.8. performance ...................................................................................... 22 2.9. power supply considerations............................................................ 23 2.10. power supply rejection ratio ......................................................... 23 2.11. reset operation ............................................................................ 23 2.12. power-down operat ion .................................................................... 23 2.13. sync operation .............................................................................. 24 2.14. serial read operation ..................................................................... 24 2.15. serial write operation ..................................................................... 24 2.16. offset calibration operation ............................................................ 25 2.17. status bits ....................................................................................... 26 2.18. board layout cons iderations .......................................................... 28 3. cs5321 pin descriptions ....................................................................... 29 power supplies ......................................................................................... 29 analog inputs ............................................................................................ 29 digital inputs ............................................................................................. 30 digital outputs .......................................................................................... 30 4. cs5322 pin descriptions ....................................................................... 31 power supplies ......................................................................................... 31 digital outputs .......................................................................................... 31 digital inputs ............................................................................................. 32 5. parameter definitions......................................................................... 34 6. package dimensions.............................................................................. 35 7. ordering information ......................................................................... 36 8. environmental, manufacturing, & handli ng information ... 36 9. revision history .................................................................................... 36
cs5321/22 ds454f2 3 list of figures figure 1. rise and fall times ................ ..................................................................... 6 figure 2. cs5321 interface timing, hbr=1 ............................................................... 6 figure 3. cs5322 filter response ........ ..................................................................... 8 figure 4. cs5322 digital filter passband ripple, f 0 = 62.5 hz .................................. 8 figure 5. cs5322 digital filter passband ripple, f 0 = 125 hz ................................... 8 figure 6. cs5322 digital filter passband ripple, f 0 = 250 hz ................................... 8 figure 7. cs5322 digital filter passband ripple, f 0 = 500 hz ................................... 9 figure 8. cs5322 digital filter passband ripple, f 0 = 1000 hz ................................. 9 figure 9. cs5322 digital filter passband ripple, f 0 = 2000 hz ................................. 9 figure 10. cs5322 digital filter passband ripple, f 0 = 4000 hz ............................... 9 figure 11. cs5322 impulse response, f 0 = 62.5 hz .................................................. 9 figure 12. cs5322 impulse response, f 0 = 1000 hz ................................................. 9 figure 13. cs5322 serial port timing ...... ................................................................ 11 figure 14. tdata setup/hold timing ......... ............................................................. 12 figure 15. drdy timing .......................................................................................... 13 figure 16. reset timing ......................................................................................... 13 figure 17. cs5321/cs5322 interface timing ........................................................... 14 figure 18. cs5321 block diagram .............. ............................................................. 16 figure 19. cs5322 block diagram .............. ............................................................. 17 figure 20. system connection diagram ... ................................................................ 19 figure 21. 4.5 voltage refer ence with two filter options .......................................... 20 figure 22. 1024 point fft plot with -20 db input, 100 hz input, ten averages 22 figure 23. 1024 point fft plot with full scale input, 100 hz input, hbr = 1, ten averages ............................................. 22 figure 24. 1024 point fft plot with full scale input, 100 hz input, hbr = 0, ten averages ............................................. 22 list of tables table 1. output coding for the cs5321 an d cs5322 combination ....................... 21 table 2. configuration data bits ............................................................................ 25 table 3. status data (from the sod pin) ............................................................... 26 table 4. bandwidth selection: truth table ............................................................ 27
cs5321/22 4 ds454f2 1. characteristics and specifications cs5321 analog characteristics (t a = (see note 1); v ss1 , v ss2 = -5 v; v dd1 , v dd2 = +5 v; vd+ = 5 v; agnd = dgnd = 0 v; hbr = v dd lpwr = 0, mclk = 1.024 mhz; device connected as shown in figure 20, cs5322 used for filtering; logic 1 = vd+, logic 0 = 0v; unless otherwise specified.) notes: 1. cs5321-bl is guaranteed from -55 o to +85 o c, cs5322-bl is guaranteed from -40 o to +85 o c. 2. f o = cs5322 output word rate. re fer to ?cs5322 filter character istics? on page 8 for details on the fir filter. 3. characterized with full scale input signal of 50 hz; fo = 500 hz. 4. characterized with input signals of 30 hz and 50 hz , each 6 db down from full scale with fo = 1000 hz. 5. specification is for the parameter over the specif ied temperature range and is for the cs5321 device only (vref = +4.5 v). it does not include th e effects of external components; ofst = 0. 6. drift specifications are guaranteed by design and/or characterization. 7. the offset after calibration specification ap plies to the effective offset voltage for a 4.5 volt input to the cs5321 modulator, but is relative to the output digital codes from the cs5322 after orcal and useor have been made active. 8. the cs5322 offset calibration is performed digitally and includes full scale ( 4.5 volts into cs5321). calibration of offsets greater than 5% of full scale will begin to su btract from th e dynamic range. parameter* cs5321 symbol min typ max unit dynamic performance dynamic range (note 2) hbr = 1 f o = 4000 hz ofst = 1 f o = 2000 hz f o = 1000 hz f o = 500 hz f o = 250 hz f o = 125 hz f o = 62.5 hz hbr = 0 f o = 4000 hz ofst = 1 f o = 2000 hz f o = 1000 hz f o = 500 hz f o = 250 hz f o = 125 hz f o = 62.5 hz dr - - 116 - - - - - - - - - - - 103 118 121 124 127 129 130 99 115 118 121 124 126 127 - - - - - - - - - - - - - - db db db db db db db db db db db db db db signal-to-distortion (note 3) hbr = 1 hbr = 0 sdr 108 110 115 120 - - db db intermodulation distortion (note 4) imd - 110 - db dc accuracy full scale error (note 5) fse - 1 - % full scale drift (note 5,6) tc fs -5- ppm/c offset (note 5) v zse -10 -mv offset after calibration (note 7) - 100 - v offset calibration range (note 8) - 100 - %f.s. offset drift (note 5,6) tc zse -60-v/c
cs5321/22 ds454f2 5 cs5321 analog characteristics (continued) notes: 9. the upper bandwidth limit is dete rmined by the cs5322 digital filter. 10. this input voltage range is for the configuratio n shown in figure 20, the system connection diagram, and applies to signal from dc to f3 hz. refer to cs5322 filter characteristics for the values of f3. 11. all outputs unloaded. all logic inputs forced to v dd or gnd respectively. 12. lpwr = 0. 13. the cs5321 power dissipation can be reduced under the following conditions: a) lpwr=1; mclk=512 khz, hbr=1 b) lwpr=1; mclk=1.024 mhz, hbr=0 14. characterized with a 100 mvp-p sine wave applied separately to each supply. * refer to parameter definitions (immediately following pin descriptions at the end of this data sheet). specifications are subject to change without notice. parameter* cs5321 symbol min typ max unit input characteristics input signal frequencies (note 9) bw dc - 1600 hz input voltage range (note 10) v in -4.5 - +4.5 v input overrange voltage (note 10) i ovr --5%f.s. power supplies dc power supply currents (note 11) lpwr = 0 positive supplies negative supplies lpwr = 1 positive supplies negative supplies - - 5.5 5.5 3.0 3.0 7.5 7.5 4.5 4.5 ma ma ma ma power consumption (note 11) normal operating mode (note12) lower power mode (note 13) p dn p dl - - 55 30 75 45 mw mw power down p d -2-mw power supply rejection (dc to 128 khz) (note 14) psr - 60 - db
cs5321/22 6 ds454f2 cs5321 switching characteristics (t a = (see note 1); v dd1 , v dd2 = 5 v 5%; v ss1 , v ss2 = -5 v 5%; inputs: logic 0 = 0 v logic 1 = v+; c l = 50 pf (note 15)) notes: 15. guaranteed by design, characterization, or test. 16. if mclk is removed, the modulat or will enter the po wer down mode. 17. excludes mclk input. mclk should be driven with a si gnal having rise and fall times of 25 ns or faster. parameter symbol min typ max units mclk frequency (note 16) f c 0.250 1.024 1.2 mhz mclk duty cycle 40 - 60 % mclk jitter (in-band) - - 300 ps rise times: any digital input (note 17) any digital output t risein t riseout - - - 50 100 200 ns ns fall times: any digital input (note 17) any digital output t fallin t fallout - - - 50 100 200 ns ns msync setup time to mclk rising t mss 20 - - ns msync hold time after mclk rising t msh 20 - - ns mclk rising to valid mflg t mfh -140255ns mclk rising to valid mdata t mdv -170300ns 4.0 v 1.0 v t fallin t risein 4.6 v 0.4 v t riseout t fallout figure 1. rise and fall times mflg mdata t mdv t mdv valid data valid data mclk t mss msync t mfh t msh figure 2. cs5321 interface timing, hbr=1
cs5321/22 ds454f2 7 cs5321 digital characteristics (t a = (see note 1); v dd1 = v dd2 = 5.0 v 5%; gnd = 0 v; measurements performed under static conditions) notes: 18. device is intended to be driven with cmos logic levels. 19. device is intended to be interfaced to cmos logic. resistiv e loads are not recommended on these pins. cs5321 recommended operation conditions (voltages with respect to gnd = 0 v, see note 20) notes: 20. the maximum voltage differential between the po sitive supply of the cs5321 and the positive digital supply of the cs5322 must be less than 0.25 v. cs5321 absolute maximum ratings * (voltages with respect to gnd = 0 v) notes: 21. transient currents of up to 100 ma will not cause scr latch up. *warning: operation beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. parameter symbol min typ max units high-level input drive voltage (note 18) v ih (v dd )-0.6 - - v low-level input drive voltage (note 18) v il --1.0v high-level output voltage iout = -40 a (note 19) v oh (v dd )-0.3 - - v low-level output voltage iout = +40 a (note 19) v ol --0.3v input leakage current i lkg --10a digital input capacitance c in -9-pf digital output capacitance c out -9-pf parameter symbol min typ max units dc supply: positive negative v dd1, v dd2 v ss1 ,v ss2 4.75 -4.75 5.0 -5.0 5.25 -5.25 v v ambient operating temperature -bl t a -55 - +85 c parameter symbol min max units dc supply: positive negative v dd1, v dd2 v ss1 ,v ss2 -0.3 +0.3 6.0 -6.0 v v input current, any pin ex cept supplies (note 21) i in -10ma output current i out -25ma total power (all supplies and outputs) p t -1w digital input voltage v ind -0.3 (v dd )+0.3 v storage temperature t stg -65 150 c
cs5321/22 8 ds454f2 cs5322 filter characteristics (t a = (see note 1); vd+ = 5.0 v; gnd = 0 v; clkin = 1.024 mhz; transfer function shown in figure 3; unless otherwise specified.) notes: 22. g sb = -130 db for all output word rates. output word rate f 0 (hz) passband f1 (hz) passband flatness r pb (db) -3db freq. f2 (hz) stopband f3 (hz) (note 22) group delay (ms) 4000 2000 1000 500 250 125 62.5 1500 750 375 187.5 93.8 46.9 23.4 0.2 0.04 0.08 0.1 0.1 0.1 0.1 1652.5 824.3 411.9 205.9 102.9 51.5 25.7 2000 1000 500 250 125 62.5 31.25 7.25 14.5 29 58 116 232 464 f1 f2 f3 f db 0 g sb -130 -3 figure 3. cs5322 filter response figure 4. cs5322 digital filter passband ripple f 0 = 62.5 hz figure 5. cs5322 digital filter passband ripple f 0 = 125 hz figure 6. cs5322 digital filter passband ripple f 0 = 250 hz
cs5321/22 ds454f2 9 figure 7. cs5322 digital filter passband ripple f 0 = 500 hz figure 8. cs5322 digital filter passband ripple f 0 = 1000 hz figure 9. cs5322 digital filter passband ripple f 0 = 2000 hz figure 10. cs5322 digital filter passband ripple f 0 = 4000 hz 1 8 15 22 29 36 43 50 57 tim e (# of o utput w ords) -5,250,000 -5,243,750 -5,237,500 -5,231,250 -5,225,000 -5,218,750 -5,212,500 -5,206,250 digital output code -5,240,723 1 8 15 22 29 36 43 50 57 time (# of output words) digital output code -5,208,328 -5,250,000 -5,243,750 -5,237,500 -5,231,250 -5,225,000 -5,218,750 -5,212,500 -5,206,250 figure 11. cs5322 impulse response, f 0 = 62.5 hz figure 12. cs5322 impulse response, f 0 = 1000 hz
cs5321/22 10 ds454f2 cs5322 power supply (t a = (see note 1); vd+ = 5 v; clkin = 1.024 mhz) cs5322 switching characteristics (t a = (see note 1); vd+ = 5 v 5%; dgnd = 0 v; inputs: logic 0 = 0 v logic 1 = vd+; c l = 50 pf (note 23) 23. guaranteed by design, characterization and/or test. parameter cs5322-bl min typ max unit power supply current: id+ (note 11) - 2.2 4 ma power dissipation: (note 11) pwdn low pwdn high - - 11 0.6 20 2.5 mw mw parameter symbol min typ max units clkin frequency f c 0.512 1.024 1.2 mhz clkin duty cycle 40 - 60 % rise times: any digital input any digital output t rise - - - 50 100 100 ns ns fall times: any digital input any digital output t fall - - - 50 100 100 ns ns serial port read timing drdy to data valid t ddv - - 25 ns rsel setup time before data valid t rss 50 - - ns read setup before cs active t rsc 20 - - ns read active to data valid t rdv - - 50 ns sclk rising to new sod bit t rdd - - 50 ns sclk pulse width high t rph 30 - - ns sclk pulse width low t rpl 30 - - ns sclk period t rsp 100 - - ns sclk falling to drdy falling t rst - - 50 ns cs high to output hi-z t rch - - 20 ns read hold time after cs inactive t rhc 20 - - ns read select setup to sclk falling t rds 20 - - ns serial port write timing write setup before cs active t wsc 20 - - ns sclk pulse width low t wpl 30 - - ns sclk pulse width high t wph 30 - - ns sclk period t wsp 100 - - ns write setup time to first sclk falling t wws 20 - - ns data setup time to first sclk falling t wds 20 - - ns write select hold time after sclk falling t wwh 20 - - ns write hold time after cs inactive t whc 20 - - ns data hold time after sclk falling t wdh 20 - - ns
cs5321/22 ds454f2 11 rsel drdy sod sclk msb-1 lsb+1 lsb t rss t ddv t rdv hi-z msb t rph t rds t rdd t rpl t rsp t rch t rst hi-z r/w cs t rsc t rhc serial port read timing (r/w = 1, cs = 0, rsel = 1 drdy does not toggle if reading status, rsel = 0) sid sclk r/w cs lsb+1 msb t wwh t wpl t wph lsb msb-1 t wsp t wws t wds t wdh t whc t wsc serial port write timing figure 13. cs5322 serial port timing
cs5321/22 12 ds454f2 cs5322 switching characteristics (continued) parameter symbol min typ max units test data (tdata) timing sync setup time to clkin rising t ss 20 - - ns sync hold time after clkin rising t sh 20 - - ns tdata setup time to clkin rising after sync t tds -20-ns tdata hold time after clkin rising t tdh -150-ns orcal setup time to clkin rising t os 20 - - ns orcal hold time after clkin rising t oh 20 - - ns drdy timing clkin rising to drdy falling t df -140-ns clkin falling to drdy rising t dr -150-ns clkin rising to error change t ec -140-ns reset timing reset setup time to clkin rising t rs 20 - - ns reset hold time after clkin rising t rh 20 - - ns sync setup time to clkin rising t ss 20 - - ns sync hold time after clkin rising t sh 20 - - ns t rdh sync orcal lsync* tdata filter valid valid t ss t sh t tds t td s t tdh samples data clkin t os t oh figure 14. tdata setup/hold timing
cs5321/22 ds454f2 13 t dr clkin sync lsync* drdy *note: for overwrite case, drdy will remain high. error t ec t df figure 15. drdy timing reset t rs t rh clkin t ss t sh sync figure 16. reset timing
cs5321/22 14 ds454f2 cs5322 switching characteristics (continued) notes: 24. if mclk is removed, the modul ator will enter the power down mode. 25. excludes mclk input. mclk should be driven with a signal having rise and fall times of 25 ns or faster. 26. only the rising edge of msync relative to mclk is used to synchronize the device. msync can return low at any time as long as it rema ins high for at least one mclk cycle. parameter symbol min typ max units mclk frequency (note 24) f c 0.512 1.024 1.1 mhz mclk duty cycle 40 - 60 % rise times: any digital input (note 25) any digital output t rise - - - 50 100 200 ns ns fall times: any digital input (note 25) any digital output t fall - - - 50 100 200 ns ns sync setup time to clkin rising t ss 20 - - ns sync hold time after clkin rising t sh 20 - - ns clkin edge to mclk edge t mss -30-ns mclk rising to valid mdata t msh -50-ns msync delay from mclk rising (note 26) t msd -90-ns t mss clkin sync lsync* mclk msync mdata mflg * internal timing signal generated in the cs5322 filter samples data t msd t msd t msh t msh valid data valid data t sh t ss figure 17. cs5321/cs 5322 interface timing
cs5321/22 ds454f2 15 cs5322 digital characteristics (t a = (see note 1); vd+ = 5.0 v 5%; gnd = 0 v; measurements performed un der static conditions) notes: 27. device is intended to be driven with cmos logic levels. 28. device is intended to be interfaced to cmos logic. resistiv e loads are not recommended on these pins. cs5322 recommended operation conditions (voltages with respect to gnd = 0v) notes: 29. the maximum voltage differential between the po sitive supply of the cs5321 and the positive digital supply of the cs5322 must be less than 0.25 v. cs5322 absolute maximum ratings * (voltages with respect to gnd = 0 v) notes: 30. transient currents of up to 100 ma will not cause scr latch up. *warning: operation beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. parameter symbol min typ max units high-level input drive voltage v ih (vd+)-0.3 - - v low-level input drive voltage v il --0.3v high-level input threshold (note 27) (vd+)-1.0 - - v low-level input threshold (note 27) - - 1.0 v high-level output voltage iout = -40 a (note 28) v oh (vd+)-0.6 - - v low-level output voltage iout = +1.6 ma (note 28) v ol --0.4v input leakage current all pins except mflg, sod i lkg --10a three-state leakage current i oz --10a digital input capacitance c in -9-pf digital output capacitance c out -9-pf parameter symbol min typ max units dc supply: (note 29) positive negative vd+ vd- 4.75 -4.75 5.0 -5.0 5.25 -5.25 v v ambient operating temperature -bl t a -40 - +85 c parameter symbol min typ max units dc supply: (note 29) positive negative vd+ vd- -0.3 0.3 - - (vd+)+0.3 -6.0 v v input current, any pin ex cept supplies (note 30) i in --10ma digital input voltage vind -0.3 - (vd+)+0.3 v storage temperature t stg -65 - 150 c
cs5321/22 16 ds454f2 2. general description the cs5321 is a fourth-order cmos monolithic analog modulator designed specifically for very high resolution measurement of signals between dc and 1600 hz. configuring the cs5321 with the cs5322 fir filter results in a high resolution a/d converter system that pe rforms sampling and a/d conversion with a dynamic range exceeding 120 db. the cs5321 uses a fourth -order oversampling ar- chitecture to achieve high resolution a/d conver- sion. the modulator consists of a 1-bit a/d converter embedded in a negative feedback loop. the modulator provides an oversampled serial bit stream at 256 kbits pe r second (hbr=1) and 128 kbits per second (hbr=0) operating with a clock rate of 1.024 mhz. figur e 18 illustrates the cs5321 block diagram. the cs5322 is a monolithic digital finite impulse response (fir) filt er with programmable decima- tion. the cs5322 and cs5321 are intended to be used together to form a unique high dynamic range adc chipset. the cs5322 provides the digital anti-alias filter for the cs5321 modulator output. the cs5322 consists of: a multi-stage fir filter, four registers (status, da ta, offset, and configura- tion), a flexible serial i nput and output port, and a 2-channel input data mul tiplexer that selects data from the cs5321 (mdata ) or user test data (tdata). the cs5322 decimates (64x to 4096x) the output to any of seven selectable up-date peri- ods: 16, 8, 4, 2, 1, 0.5 and 0.25 milliseconds. data is output from the digital filter in a 24-bit serial for- mat. figure 19 illustra tes the cs5322 block dia- gram. figure 18. cs5321 block diagram ainr v dd1 osc. detect ain+ ain- vref+ vref- d/a a/d digital control mdata mdata clock generation msync mclk hbr mflg ofst lpwr v ss1 agnd v dd2 v ss2 dgnd
cs5321/22 ds454f2 17 sod sid tdata mdata csel pwdn orcal useor decc decb deca sclk clkin reset sync mflg drdy msync mclk h/s cs r/w error rsel co n fig reg config mux status reg bit select mux bit select data reg fir2 fir3 fir1 data mux control figure 19. cs5322 block diagram
cs5321/22 18 ds454f2 2.1 analog input the cs5321 modulator uses a switched capacitor architecture for its signal and voltage reference in- puts. the signal input uses three pins; ainr, ain+, and ain-. the ain- pin acts as the return pin for the ainr and ain+ pins . the ainr pin is a switched capacitor "rough charge" input for the ain+ pin. the input impedance for the rough charge pin (ainr) is 1/fc where f is two times the modulator sampling clock ra te and c is the internal sampling capacitor (about 40 pf). using a 1.024 mhz master clock (hbr = 1) yields an input im- pedance of about 1/(512 khz)x(40 pf) or about 50 k ? . internal to the chip th e rough charge input pre- charges the sampling capa citor used on the ain+ input, therefore the eff ective input impedance on the ain+ pin is orders of magnitude above the im- pedance seen on the ainr pin. the analog input structure inside the vref+ pin is very similar to the ainr pin but includes addition- al circuitry whose operating current can change over temperature and from device to device. there- fore, if gain accuracy is important, the vref+ pin should be driven from a low source impedance. the current demand of the vref+ pin will produce a voltage drop of approxima tely 45 mv across the 200 ? source resistor of figure 20 and figure 21 option a with mclk = 1.024 mhz, hbr = 1, and temperature = 25 c. when the cs5321 modulator is operated with a 4.5 v reference it wi ll accept a 9 v p- p input signal, but modulator loop stab ility can be adversely affected by high frequency out-of-band signals. therefore, input signals must be band- limited by an input fil- ter. the -3 db corner of the input filter must be equal to the modulator sampling clock divided by 64. the modulator sampling clock is mclk/4 when hbr = 1 or mclk /8 when hbr = 0. with mclk = 1.024 mhz, hbr = 1, the modulator sampling clock is 256 khz which requires an input filter with a -3 db corner of 4 khz. the bandlimit- ing may be accomplished in an amplifier stage ahead of the cs5321 modulator or with the rc in- put filter at th e ain+ and ainr input pins. the rc filter at the ain+ and ai nr pins is recommended to reduce the "charge kick " that the driving ampli- fier sees as th e switched capacitor sampling is per- formed. figure 20 illustrates the cs5321 and cs5322 sys- tem connections. the i nput components on ainr and ain+ should be iden tical values for optimum performance. in choosi ng the components the ca- pacitor should be a minimum of 0.1 f (c0g di- electric ceramic prefer red). for minimum board space, the rc components on the ainr input can be removed, but this will force the driving amplifi- er to source the full dynamic charging current of the ainr input. this can in crease distortion in the driving amplifier and re duce system performance. in choosing the rc filter components, increasing c and minimizing r is pref erred. increasing c reduc- es the instantaneous volta ge change on the pin, but may require paralleling capacitors to maintain smaller size (the recommended 0.1 f c0g ceram- ic capacitor is larger than other similar-valued ca- pacitors with different di electrics). larger resistor values will increase the voltage drop across the re- sistor as the recharging current charges the switched capacitor input. 2.2 the ofst pin the cs5321 modulator can produce "idle tones" which occur in the passband when the input signal is steady state dc signal within about 50 mv of bipolar zero. in the cs5321 these tones are about 135 db down from full scale. the user can force these idle tones "out-of-band" by adding 100 mv of dc offset to th e signal at th e ain input. alternately, if the user circuitry has a low offset voltage such that the input signal is within 50 mv of bipolar zero when no ac signal is present, the ofst pin on the cs5321 can be activated. when ofst = 1, +100 mv of input referred offset will be
cs5321/22 ds454f2 19 added internal to the cs5321 and guarantee that any idle tones present will lie out-of-band. the user should be certain that wh en ofst is active (ofst =1) that the offset voltage generated by the user cir- cuitry does not negate the offset added by the ofst pin. 2.3 input range and overrange conditions the analog input is applied to the ain+ and ainr pins with the ain- pin c onnected to gnd. the in- put is fully differential but for proper operation the ain- pin must remain at gnd potential. the analog input span is defined by the voltage ap- plied between the vref+ and vref- input pins. see the voltage reference s ection of this data sheet for voltage reference requirements. the modulator is a fourth order delta-sigma and is therefore conditionally st able. the modulator may go into an oscillatory condition if the analog input is overranged. input signa ls which exceed either plus or minus full scale by more than 5 % can intro- duce instability in the m odulator. if an unstable condition is detected, the modulator will be re- duced to a first order syst em until loop stability is achieved. if this occurs the mflg pin will transi- tion from a low to a high a nd result in an error bit being set in the cs5322. the input signal must be reduced to within the full scale range of the con- verter for at least 32 mclk cycles for the modula- tor to recover from this error condition. tdata vd+ dgnd +5 v digital supply 0.01 f sid sod sclk cs r/w drdy rsel error csel pwdn useor orcal deca decb decc clkin sync serial data interface unused logic inputs must be connected to dgnd or vd+ cs5322 control hardware vd+ dgnd +5 v digital supply 0.01 f h/s reset 3 2 11 21 20 25 24 26 1 28 22 27 23 12 13 14 15 19 18 17 16 4 9 8 gnd1 vref+ v dd2 v ss2 v dd1 0.1 f 0.1 f -5v analog supply +5v analog supply cs5321 0.1 f test data + 10 f + 10 f 2 22 21 5 1 gnd2 v ss1 0.1 f 3 4 gnd9 gnd10 gnd8 +4.5v vref 0.1 f 68 f + tant. 19 16 15 vref- 6 ain+ 0.1 f 9 signal source cog ain- 8 ainr 10 gnd5 12 gnd6 13 gnd3 7 gnd4 11 14 gnd7 402 msync 5 msync 25 mflg 6 mflg 24 mclk 7 mclk 20 mdata 10 mdata 18 gnd11 23 ofst 28 lpwr 27 hbr 26 control logic clock source 17 mdata 200 0.1 f cog 402 ? ? ? figure 20. system connection diagram
cs5321/22 20 ds454f2 2.4 voltage reference the cs5321 is designed to operate with a voltage reference in the range of 4.0 to 4.5 volts. the volt- age reference is applied to the vref+ pin with the vref- pin connected to the gnd. a 4.5 v refer- ence will result in the best s/n performance but most 4.5 v references requi re a power supply volt- age greater than 5.0 v fo r operation. a 4.0 v refer- ence can be used for those applications which must operate from only 5.0 v suppl ies, but will yield a s/n slightly lower (1-2 db) than when using a 4.5 v reference. the voltage reference should be de- signed to yield less than 2 vrms of noise in band at the vref+ pin of the cs5321. the cs5322 filter selection will determine the bandwidth over which the voltage reference noi se will affect the cs5321/22 dynamic range. for a 4.5 v reference, th e lt1019-4.5 voltage ref- erence yields low enough noi se if the output is fil- tered with a low pass rc filter as shown in figure 21 option a. the filter in figure 21 option a is ac- ceptable for most spectr al measurement applica- tions, but a buffered vers ion with lower source impedance (figure 21 opti on b) may be preferred for dc-measurement applic ations. due to its dy- namic (switched-capacitor) input the input imped- ance of the +vref pin of the cs5321 will change any time mclk or hbr is changed. therefore the current required from th e voltage reference will change any time mclk or hbr is changed. this can affect gain accuracy due to the high source im- pedance of the filter resi stor in figure 20 and fig- ure 21 option a. if gain error is to be minimized, especially when mclk or hbr is changed, the voltage reference should have lower output imped- ance. the buffer of figure 21 option b offers lower output impedance and will exhibit better system gain stability. 2.5 clock source for proper operation, the cs5321 must be provided with a cmos-compatible clock on the mclk pin. the mclk for the cs5321 is usually provided by the cs5322 filter. mclk is usually 1.024 mhz to set the seven selectable output word rates from the cs5322. the mclk frequency can be as low as 250 khz and as high as 1.2 mhz. the choice of clock frequency can affect performance; see the performance section of th e data sheet. the clock 0.1 f +9 to 15v 10 ? lt1019-4.5 200 ? + - 49.9 ? 1k ? 100 ? 1k ? 10k ? 100 f al 100 f al +9 to 15v 0.1 f + + 68 f tant + 0.1 f 68 f + to vref+ to vref+ lt1007 option a option b figure 21. 4.5 voltage reference with two filter options
cs5321/22 ds454f2 21 must have less than 300 ps jitter to maintain data sheet performance from the device. the cs5321 is equipped with loss of cl ock detection circuitry which will cause the cs 5321 to enter a powered- down state if the mclk is removed or reduced to a very low frequency. the hbr pin on the cs5321 modifies the sampling clock rate of the modulator. when hbr = 1, the modulat or sampling clock will be at mclk/4; with h br = 0 the modulator sam- pling clock will be at mc lk/8. the chip set will ex- hibit about 3 db less s/ n performance when the hbr pin is changed from a logic "1" to a logic "0" for the same output word rate from the cs5322. 2.6 low power mode the cs5321 includes a low power operating mode (lpwr =1). when operate d with lpwr = 1, the cs5321 modulator sampling cl ock must be restrict- ed to rates of 128 khz or less. operating in low power mode with modulator sample rates greater than 128 khz will greatly degrade performance. 2.7 digital interface and data format the mclk signal (normally 1.024 mhz) is divid- ed by four, or by eight in side the cs5321 to gener- ate the modulator oversam pling clock. the hbr pin determines whether the clock divider inside the cs5321 divides by four (hbr =1) or by eight (hbr = 0). the modulato r outputs a ones density bit stream from it s mdata and mdata pins pro- portional to the analog input signal, but at a bit rate determined by the modulat or over sampling clock. for proper synchronization of the bitstream, the cs5321 must be furnished with an msync signal prior to data conversi on. the msync signal, gen- erated by the cs5322, resets the mclk counter-di- vider in the cs5321 to the correct phase so that the bitstream can be prope rly sampled by the cs5322 digital filter. when operated with the cs5322 digital filter the output codes from the cs5321/22 will range from approximately decimal -5,242,880 to +5,242,879 for an input to the cs5321 of 4.5 v. table 1 illus- trates the output coding for various input signal am- plitudes. note that with a signal input defined as a full scale signal (4.5 v wi th vref+ = 4.5 v) the cs5321/22 chipset does not ou tput a full scale dig- ital code of 8,388,607 but is scaled to a lower value to allow some overrange capability. input signals can exceed the defined full scale by up to 5% and still be converted properly. modulator input signal cs5322 filter output code hex decimal > (+vref + 5%) error flag possible (+vref + 5%) 53ffff(h) +5505023 +vref 4fffff(h) +5242879 0v 000000(h) 0 -vref b00000(h) -5242880 - (+vref +5%) ac0000(h) -5505024 > - (+vref +5%) error flag possible table 1. output coding for the cs5321 and cs5322 combination
cs5321/22 22 ds454f2 2.8 performance figure 22, 23 and 24 illustra te the spectral perfor- mance of the cs5321/22 and chipset when operat- ing from a 1.024 mhz master clock. ten 1024 point ffts were averaged to produce the plots. figure 22 illustrates the chip set with a 100 hz, -20 db input signal. the sa mple rate was set at 1 khz. dynamic range is 122 db. the dynamic range calculated by the test soft-ware is reduced somewhat in figures 23 and 24 because of jitter in the signal test oscillator. jitter in the 100 hz signal source is interpreted by the signal processing software to be increased noise. the choice of master cl ock frequency will affect performance. the cs5321 will exhibit the best sig- nal to distortion performa nce with slower modula- tor sampling clock rates as slower sample rates allow more time for amplifier settling. for lowest offset drift, the cs5321 should be oper- ated with mclk = 1.024 mhz and hbr = 1. slow- er modulator sampling cl ock rates will exhibit more offset drift. changing mclk to 512 khz (hbr = 1) or changing hbr to zero (mclk = 1.024 mhz) will cause the dr ift rate to double. off- set drift is not lin ear over temperatur e so it is diffi- cult to specify an exact drift rate. offset drift characteristics vary from pa rt to part and will vary as the power supply voltages vary. therefore, if the cs5321 is to be used in precision dc measurement applications where offset drift is to be minimized, the power supplies should be well regulated. the cs5321 will exhibit about 6 ppm/c of offset drift with mclk = 1 and hbr = 1. gain drift of the cs5321 itself is about 5 pp m/c and is not affected by either modulator sample rate or by power supply variation. figure 22. 1024 point fft plot with -20 db input, 100 hz input, ten averages dynamic range = 122.0 db hbr = 1 ofst = 0 lpwr = 0 0 500 0 -20 -40 -60 -80 -100 -120 -140 -160 -180 figure 23. 1024 point fft plot with full scale input, 100 hz input, hbr = 1, ten averages s/d = 116.0 db s/n = 118.4 db s/n+d = 114.2 db hbr = 1 ofst = 0 lpwr = 0 0 500 0 -20 -40 -60 -80 -100 -120 -140 -160 -180 see text figure 24. 1024 point fft plot with full scale input, 100 hz input, hbr = 0, ten averages 0 500 0 -20 -40 -60 -80 -100 -120 -140 -160 -180 s/d = 122.7 db s/n = 117.1 db s/n+d = 116.4 db hbr = 0 ofst = 0 lpwr = 0 see text
cs5321/22 ds454f2 23 2.9 power supply considerations the system connection di agram, figure 20, illus- trates the recommended power supply arrange- ments. there are two pos itive power supply pins for the cs5321 and two negative power supply pins. power must be supplie d to all four pins and each of the supply pins should be de-coupled with a 0.1 f capacitor to the nearest ground pin on the device. when used with the cs532 2 digital filter, the max- imum voltage differential between the positive sup- plies of the cs5321 and th e positive digital supply of the cs5322 must be less than 0.25 v. operation beyond this constraint may result in loss of analog performance in the cs5321/22 system perfor- mance. many seismic or portable data acquisition systems are battery powered and utilize dc-dc converters to generate the necessary supply voltages for the sys- tem. to minimize the effects of power supply inter- ference, it is desirabl e to operate the dc-dc converter at a frequency which is rejected by the digital filter, or locked to the modulator sample clock rate. a synchronous dc-dc converter, whose operating frequency is derived fr om the 1.024 mhz clock used to drive the cs5322, will minimize the poten- tial for "beat frequenc ies" appearing in the pass- band between dc and the co rner frequency of the digital filter. 2.10 power supply rejection ratio the psrr of the cs5321 is frequency dependent. the cs5322 digital filter attenuation will aid in re- jection of power supply noise for frequencies above the corner freque ncy setting of the cs5322. for frequencies between dc and the corner frequen- cy of the digital filter, the psrr is nearly constant at about 60 db. 2.11 reset operation the reset pin puts the cs5322 into a known ini- tialized state. reset is recognized on the next clkin rising edge after the reset pin has been brought high (reset=1). all internal logic is ini- tialized when reset is active. normal device operation begins on the second clkin rising edge afte r reset is brought low. the cs5322 will remain in an idle state, not per- forming convolutions, unt il triggered by a sync event. a reset operation clears memory, sets the data output register, offset regist er, and status flags to all zeroes, and sets the confi guration register to the state of the corresponding hardware pins (pwdn, orcal, decc, decb, deca, useor, and csel). the reset state is entered on power on, in- dependent of the reset pin. if reset is low, the first clkin will exit the power on reset state. 2.12 power-down operation the pwdn pin puts the cs5322 into the power- down state. the power-down state is entered on the first clkin rising edge after the pwdn pin is brought high. while in the power-down state, the mclk and msync signals to the cs5321 analog modulator are held low. the loss of the mclk sig- nal to the modulator cause s it to power-down. the signals on the mdata a nd mflg pins are ig- nored. the serial interface of the cs5322 remains active allowing read and wr ite operations. informa- tion in the data register, offset register, configura- tion register, and convolution data memory are maintained during power- down. the internal con- troller requires 64 clock cy cles after pwdn is as- serted before clkin stops. the cs5322 exits the power-down state on the first clkin rising edge afte r the pwdn pin is brought low. the cs5322 then enters an idle state until trig- gered by a sync event.
cs5321/22 24 ds454f2 to avoid possible high curr ent states while in the power down state, the following conditions apply: 1) clkin must be active fo r at least 64 clock cy- cles after pwdn entry. 2) csel and tdata must not both be asserted high. 2.13 sync operation the sync pin is used to start convolutions and synchronize the cs5322 a nd cs5321 to an external sampling source or timing reference. the sync event is recognized on th e first clkin rising edge after the sync pin goe s high. sync may remain high indefinitely. only the sequence of sync ris- ing followed by clkin rising generates a sync event. the sync event aligns the output sample and causes the filter to begi n convolutions. the first sync event causes an immediate drdy provided drdy is low. subsequent data ready events will occur at a rate determined by the decimation rate inputs decc, decb, a nd deca. multiple sync events can be applied wi th no effect on operation if they are perfectly timed according to the decima- tion rate. any sync event not in step with the dec- imation rate will cause a realignment and loss of data. 2.14 serial read operation serial read is used to obtain status or conversion data. the cs , r/w , sclk, rsel, and sod pins control the read operation. the serial read opera- tion is activated when cs goes low (cs =0) with the r/w pin high (r/w =1). the rsel pin selects be- tween conversion data (data register) or status in- formation (status register). the selected serial bit stream is output on the sod (serial output data) pin. on read select, sclk can ei ther be high or low, the first bit appears on the sod pin and should be latched on the falling edge of sclk. after the first sclk falling edge, each sclk rising edge shifts out a new bit. status r eads are 16 bits, and data reads are 24 bits. both streams are supplied as msb first, lsb last. in the event more sclk pulses are supplied than necessary to clock out th e requested information, trailing zeroes will be output for data reads and trailing lsb?s for status re ads. if the read operation is terminated before all th e bits are read, the inter- nal bit pointer is reset to the msb so that a re-read will give the same data as the first read, with one exception. the status erro r flags are cleared on read and will not be available on a re-read. the status error flags must be read before entering the power-down state. if an error has occurred be- fore entering powerdown a nd the status bit (er- ror) has not been read, the status bits (error, overwrite, mflg, ac c1 and acc2) may not be cleared on status read s. upon exiting the power- down state and entering normal operation, the user may be flagged that an error is still present. the sod pin floats when read operation is deacti- vated (r/w =1, cs =1). this enables the sid and sod pins to be tied togeth er to form a bi-direction- al serial data bus. there is an internal nominal 100 k ? pull-up resistor on the sod pin. 2.15 serial write operation serial write is used to write data to the configura- tion register. the cs , r/w , sclk and sid pins control the serial write operation. the serial write operation is activated when cs goes low (cs =0) with r/w pin low (r/w =0). serial input data on the sid pin is sampled on the falling edge of sclk. the i nput bits are stored in a temporary buffer unt il either the write operation is terminated or 8 bits have been received. the data is then parallel loaded into the configuration register. if fewer than 8 bi ts are input before the write termi- nation, the other bits may be indeterminate.
cs5321/22 ds454f2 25 note that a write will occur when cs = 0 and r/w = 0 even if sclk is not toggled. failure to clock in data with the appropria te number of sclks can leave the configuration regi ster in an indeterminate condition. the serial bit stream is received msb first, lsb last. the order of the in put control data is pwdn first, followed by orcal, useor, csel, re- served, decc, decb, and deca. the configura- tion data bits are defined in table 2. the configuration data controls device operation only when in the software mode , i.e., the h/s pin is low (h/s = 0). the reserved configuration data bit must always be written low. 2.16 offset calibration operation the offset calibration routine computes the offset produced by the cs5321 modulator and stores this value in the offset regist er. the useor pin or bit determines if the offset register data is to be used to correct output words. after power is applied to the chip set the cs5322 must be reset. to begin an offset calibration, the cs5321 analog input must represent the offset val- ue. then in software mode (h/s = 0) the orcal bit must be toggled from a low to a high. in hard- ware mode the orcal pin must be toggled low for at least one clkin cy cle, then taken high (ex- cept when orcal = 1 and the cs5322 is reset as this toggles the orca l internally). after or- cal has been toggled, the sync signal must be applied to the cs5322. the fi lter settles on the in- put value in 56 output word s. the output word rate is determined by the stat e of the decimation rate control pins, decc, de cb, and deca. on the 57th output word, the cs5322 issues the or- cald status flag, outputs the offset data sample, and internally loads the offset register. during cal- ibration, the offset register value is not used. if useor is high (useor=1), subsequent sam- ples will have the offset subtracted from the output. the state of useor must remain high for the com- plete duration of the convol ution cycle. if useor is low (useor=0), the out put word is not correct- ed, but the offset register retains its value for later use. the results of the last calibration will be held in the offset regi ster until the end of a new calibra- tion, or until the cs5322 is reset using the reset pin. useor does not alter th e offset register value, only its usage. to restart a calibrati on, orcal and sync must be taken low for at least one clkin cycle. or- cal must then be taken high. the calibration will restart on the next sync event. if the orcal pin remains in a high state, only a single calibration will start on the first sync signal. input bit # equivalent hardware function description 1 (msb) pwdn standby mode 2 orcal self-offset calibration 3 useor use offset register 4 csel channel select 5 reserved factory use only 6 decc filter bw selection 7 decb filter bw selection 8 (lsb) deca filter bw selection table 2. configuration data bits
cs5321/22 26 ds454f2 2.17 status bits the status register is a 16-bit register which al- lows the user to read th e flags and configuration settings of the cs5322. ta ble 3 documents the data bits of the status register. the error bit and error pin value are the or?ed result of overw rite, mflg, acc1, and acc2. the error bit is active high whenever any of the four error bits are set due to a fault con- dition. the error pin output is active low and has a nominal 100 k ? internal pull-up resistor. the overwrite bit is set when new conversion data is ready to be loaded into the data register, but the previous data was not completely read out. this can occur on either of tw o conditions: a read oper- ation is in progress or a read operation was started, then aborted, and not co mpleted. these two condi- tions are data read attempts. the attempt is identi- fied by the first sclk lo w edge (msb read) of a data register read. if a data register read is not at- tempted, the cs5322 assumes that data is not want- ed and does not assert overwrite, and the old data is over-written by th e new data. on an over- write condition, the old partially read data is pre- served, and the new data word is lost. status reads have no ef fect on overwrite assert operations. the overwrite bit is cleared on a status register read or reset. the mflg error bit reflects the cs5321 mflg signal. any high leve l on the cs5322 mflg pin will set the mflg status bit. the bit is cleared on a status register read or reset operation, only if the mflg pin on the cs5322 has returned low. a in- ternal nominal 100 k ? pulldown resistor is on the mflg pin. the accumulator error bits , acc1 and acc2, indi- cate that an underflow or overflow has occurred in the fir1 filter for acc1, or the fir2 and fir3 fil- ters for acc2. both erro rs are cleared on a status read, provided the error conditions are no longer output bit # function description 1 (msb) error detects one of the errors below 2 overwrite error o verwrite error 3 mflg error modulator flag error 4 acc1 error accumulator 1 error 5 acc2 error accumulator error 6 drdy data ready 7 1sync first sample after sync 8 orcald offset calibration done 9 pwdn standby mode 10 orcal self-offset calibration 11 useor use offset register 12 csel channel select 13 reserved factory use only 14 decc bandwidth selection status 15 decb bandwidth selection status 16 deca bandwidth selection status table 3. status data (from the sod pin)
cs5321/22 ds454f2 27 present. in normal opera tion the acc1 error will only occur when the input data stream to fir1 is all 1?s for more than 32 bits. the acc2 error cannot occur in normal operation. the drdy bit reflects th e state of the drdy pin. drdy rising edge indicates that a new data word has been loaded into the data register and is avail- able for reading. drdy wi ll fall after the sclk falling edge that reads the data register lsb. if no- data read attempt is ma de, drdy will pulse low for 1/2 clkin cycle, provi ding a positive edge on the new data availability. in the overwrite case, drdy remains high because new data is not loaded at the normal end of conversion time. the 1sync status bit provi des an indication of the filter group delay. it goe s high on the second output sample after sync and is valid for only that sam- ple. for repetitive sync operations, sync must run at one fourth the output word rate or slower to avoid interfering with the 1sync operation. with these slower repetitive sync?s or non-periodic sync?s separated by at least three output words, 1sync will occur on the second output sample af- ter sync. orcald indicates that ca libration of the offset register is complete and the offset sample is avail- able in the output register . this flag is high only during that sample and is otherwise low. the remaining five stat us bits (pwdn, orcal, useor, csel, reserved, decc, decb, and de- ca) provide configuration readback for the user. these bits echo the cont rol source for the cs5322 such that in the hardware mode (h/s =1), they fol- low the corresponding i nput pins. in host mode (h/s =0) they follow the corresponding configura- tion bits. a brief explanation of the eight bits are as follows: pwdn - when high, indicates that the cs5322 is in the power-down state. orcal - when high, indicates a potential calibra- tion start. useor - when high, indicates the offset register is used. during calibration, this bit will read zero indi- cating the offset register is not being used during cal- ibration. csel- when high, tdata is selected as the filter source. when low, the mdata output signal from the cs5321 is selected as the input source to the fil- ter. reserved - always read low. decc, decb, and deca - indicate the decimation rate of the filter and are defined in table 4. decc decb deca output word rate (hz) clocks filter output 0 0 0 62.5 16384 0 0 1 125 8192 0 1 0 250 4096 0 1 1 500 2048 1 0 0 1000 1024 1 0 1 2000 512 1 1 0 4000 256 1 1 1 reserved - table 4. bandwidth selection: truth table
cs5321/22 28 ds454f2 2.18 board layout considerations all of the 0.1 f filter capacitors on the power sup- plies, ain+, and ainr, should be placed very close to the chip and c onnect to the nearest ground pin on the device . the capacitors between vref+ and vref- should be located as close to the chip as possible. the 0.l f capacitors on the ain+ and ainr pins should be placed with their leads on the same axis, not side-by-side . if these capacitors are placed side-by-side their el ectric fields can interact and cause increased dist ortion. the chip should be surrounded with a ground plan e. trace fill should be used around the analog input components.
cs5321/22 ds454f2 29 3. cs5321 pin descriptions power supplies v dd1 ? positive power one, pin 2 positive supply voltage. nominally +5 volts. v dd2 ? positive power two, pin 22 positive supply voltage. nominally +5 volts. v ss1 ? negative power one, pin 3 negative supply voltage. nominally -5 volts. v ss2 ? negative power two, pin 21 negative supply voltage. nominally -5 volts. gnd1 through gnd11 ? ground, pins 1, 4, 7, 11, 12, 13, 14, 15, 16, 19, 23. ground reference. analog inputs ain+ - positive an alog input, pin 9 nominally 4.5v ain- - negative an alog input, pin 8 this pin is tied to ground.
cs5321/22 30 ds454f2 ainr - analog i nput rough, pin 10 allows a non-linear current to bypass the main ex ternal anti-aliasing filt er which if allowed to happen, would cause harmonic distortion in the modulator. please refer to the system connection diagram and the analog input and voltage reference s ection of the data sheet for recommended use of this pin. vref+ ? positive voltage reference input, pin 5 this pin accepts an external +4.5 v voltage reference. vref- ? negative voltage reference input, pin 6 this pin is tied to ground. digital inputs mclk ? clock input, pin 20 a cmos-compatible clock input to this pi n (nominally 1.024 mhz) provides the necessary clock for operation of the modulator and data output portions of the a/d converter. mclk is normally supplied by the cs5322 msync ? modulator sync, pin 25 a transition from a low to high level on this input will re-initialize the cs5321. msync resets a divider-counter to align the mdata output bit stream from the cs5321 with the timing inside the cs5322. ofst - offset, pin 28 when high, adds approxima tely 100 mv of input referred of fset to guarantee that any zero input limit cycles are out of band if pr esent. when low, zero offset is added. lpwr - low powe r mode, pin 27 the cs5321 power dissipation ca n be reduced from its nomin al value of 55 mw to 30 mw under the following conditions: lpwr=1; mclk = 512 khz, hbr=1; or lpwr=1; mclk = 1.024 mhz, hbr=0 hbr ? high bit rate, pin 26 selects either 1 ? 4 mclk (hbr=1) or 1 ? 8 mclk (hbr=0) for the modulator sampling clock. digital outputs mdata ? modulator da ta output, pin 18 data will be presented in a one-bit serial da ta stream at a bit rate of 256 khz (hbr=1) or 128 khz (hbr=0) with mclk operating at 1.024 mhz. mdata ? modulator data output, pin 17 inverse of the mdata output. mflg ? modulator flag, pin 24 a transition from a low to high level signals that the cs5321 m odulator is unstable due to an overrange on the analog input
cs5321/22 ds454f2 31 4. cs5322 pin descriptions power supplies vd+ ? positive digita l power, pin 8, 21 positive digital supply voltage. nominally +5 volts. dgnd ? digital ground, pin 9, 20 digital ground reference. digital outputs mclk ? modulator cl ock output, pin 7 a cmos-compatible clock output (nominally 1.024 mhz) that provi des the necessary clock for operation of the modulator. msync ? modulator sync, pin 5 the transition from a low to high level on this output will re-initialize the cs5321. error - error flag, pin 23 this signal is the output of an open pull-up nor ga te with a nominal 100 k ? pull-up resistor to which the error status data (overwrite error, mflg error, acc1 error and acc2 error) are inputs. when low, it notifies the host proc essor that an error condition exists. the error signal can be wire or?d together with other filters? outputs. th e value of the internal pull-up resistor is 100 k ? . drdy - data ready, pin 22 when high, data is ready to be shifted out of the serial port data register. top view 22 20 24 19 21 23 25 327 2 426 28 1 12 14 16 18 13 15 17 8 6 10 5 7 9 11 chip select cs frame sync sync r/ w read/write clock input clkin rsel register select reset reset sclk serial clock modulator sync msync sid serial input data modulator flag mflg sod serial output data modulator clock mclk cs5322 error error flag positive digital power vd+ drdy data ready digital ground dgnd vd+ positive digital power modulator data mdata dgnd digital ground test data tdata orcal offset calibration channel select csel deca decimation rate control hardware/software mode h/ s decimation rate control power down pwdn decb decc decimation rate control useor use offset register
cs5321/22 32 ds454f2 sod - serial output data, pin 24 the output coding is 2?s compleme nt with the data bits presen ted msb first, lsb last. data changes on the rising edge of sc lk. an internal nominal 100 k ? pull-up resistor is included. digital inputs mdata ? modulator data, pin 10 data will be presented in a one-bit serial da ta stream at a bit rate of 256 khz; (clkin = 1.024 mhz). tdata - test data, pin 11 input for user test data. mflg ? modulator flag, pin 6 a transition from a low to high level signals that the cs5321 m odulator is unstable due to an over-range on the analog input. a status bit will be set in the digital filt er indicating an error condition. an internal nominal 100 k ? pull-down resistor included on the input pin. reset - filter reset, pin 4 performs a hard reset on the chip, all registers and accumula tors are cleared. all signals to the device are locked out except clki n. the error flags in the status register are set to zero and the data register and offset re gister are set to zero. the confi guration register is set to the values of the corresponding input pins. sync must be applied to resume convol utions after reset deasserts. clkin - clock input, pin 3 a cmos-compatible clock input to this pi n (nominally 1.024 mhz) provides the necessary clock for operation the modulator and filter. sync - frame sync, pin 2 conversion synchronization input. this signal sy nchronizes the start of the filter convolution. more than one sync signal can occur with no eff ect on filter perfor mance, providing the sync signals are perfectly timed at inte rvals equal to the output sample period. csel - channel select, pin 12 when high, information on the tdata pin is presen ted to the digital filter. a low causes data on the mdata input to be pres ented to the digital filter. pwdn - powerdown, pin 14 powers down the filter when ta ken high. convolution cycles in th e digital filter and the mclk signal are stopped. the registers ma intain their data and the se rial port remains active. sync must be applied to resume c onvolutions after pwdn deasserts. deca - decimation rate control, pin 18 see table 4. decb - decimation rate control, pin 17 see table 4.
cs5321/22 ds454f2 33 decc - decimation rate control, pin 16 see table 4. h/s - hardware/software mode select, pin 13 when high, the device pins cont rol device operation; when low, the value entered by a prior configuration write cont rols device operation. cs - chip select, pin 1 when high, all signal acti vity on the sid, r/w and sclk pins is ignored. the drdy and error signals indicate the status of the chip?s internal operation. r/w - read/write, pin 28 used in conjunction with cs such that when both signals are lo w, the filter inputs data from the sid pin on the falling edge of sclk. if cs is low and r/w is high, the filter outputs data on the sod pin on the risi ng edge of sclk. r/w low floats the sod pi n allowing sid and sod to be tied together, forming a bidirectional serial data bus. sclk - serial clock, pin 26 clock signal generated by host pr ocessor to either input data on the sid input pin, or output data on the sod output pin. for write, data must be valid on the sid pin on the falling edge of sclk. data changes on the sod pi n on the rising edge of sclk. sid - serial da ta input, pin 25 data bits are presented msb first, lsb last. data is latched on the falling edge of sclk. rsel - register select, pin 27 selects conversion data when hi gh, or status data when low. useor - use offset register, pin 15 use offset register value to co rrect output words wh en high. output words will not be offset corrected when low. orcal - offset regist er calibrate, pin 19 initiates an offset calibration cycle when sy nc goes high after orcal has been toggled from low to high. the offset value is output on the 57th word following sync. subsequent words will have their offset co rrection controlled by useor.
cs5321/22 34 ds454f2 5. parameter definitions dynamic range the ratio of the full-scale (rms) signal to the broadband (rms) noise signal. broadband noise is measured with the input grounded within the bandwidth of 1 hz to f 3 hz (see ?cs5322 filter characteristics? on page 8). units in db. signal-to-distortion the ratio of the full-scale (rms) signal to the rms sum of all harmonics up to f 3 hz. units in db. intermodulation distortion the ratio of the rms sum of the two test frequencies (30 and 50 hz) which are each 6 db down from full-scale to the rms sum of all intermodul ation components within the bandwidth of dc to f 3 hz. units in db. full scale error the ratio of the difference betw een the value of the voltage re ference and analog input voltage to the full scale span (two times the voltage re ference value). this ratio is calculated after the effects of offset and the external bias com ponents are removed and th e analog input voltage is adjusted. measurement of this pa rameter uses the circuitry illust rated in the system connection diagram. units in %. full scale drift the change in the full scale value with temperature. units in %/ c. offset the difference between the analog ground and the analog voltage necessary to yield an output code from the cs5321/22 of 00 0000(h). measurement of this parameter uses the circuit configuration illustrated in the syst em connection diagram. units in mv. offset drift the change in the offset value with temperat ure. measurement of this parameter uses the circuit configuration illustrated in th e system connection diagram. units in v/ c.
cs5321/22 ds454f2 35 6. package dimensions inches millimeters dim min max min max a 0.165 0.180 4.043 4.572 a1 0.090 0.120 2.205 3.048 b 0.013 0.021 0.319 0.533 d 0.485 0.495 11.883 12.573 d1 0.450 0.456 11.025 11.582 d2 0.390 0.430 9.555 10.922 e 0.485 0.495 11.883 12.573 e1 0.450 0.456 11.025 11.582 e2 0.390 0.430 9.555 10.922 e 0.040 0.060 0.980 1.524 jedec #: ms-018 28l plcc package drawing d1 d e1 e d2/e2 b e a1 a
cs5321/22 36 ds454f2 7. ordering information 8. environmental, manufact uring, & handling information * msl (moisture sensitivity level) as specified by ipc/jedec j-std-020. 9. revision history model temperature package cs5321-bl -55 to +85 c 28-pin ssop CS5321-BLZ (lead free) cs5322-bl -40 to +85 c cs5322-blz (lead free) model number peak reflow temp msl rating* max floor life cs5321-bl 225 c 2365 days CS5321-BLZ (lead free) 260 c cs5322-bl 225 c cs5322-blz (lead free) 260 c revision date changes pp3 oct 2003 initial release. f1 aug 2005 update ordering information. msl data added. change cs5321 t a spec to -40 to +85 degrees. f2 sep 2005 change cs5321 t a spec to -55 to +85 degrees. contacting cirrus logic support for all product questions and i nquiries contact a cirrus logic sales representative. to find the one nearest to you go to www.cirrus.com important notice cirrus logic, inc. and its subsidiaries (?cirrus?) believe that the information contained in this document is accurate and reli able. however, the information is subject to change without notice and is provided ?as is? without warranty of any kind (express or implied). customers are advised to ob tain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold s ubject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liabil ity. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for in fringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or impli ed under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the inf ormation contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications us ing semiconductor products may invo lve potential risks of death, personal injury, or severe prop- erty or environmental damage (?critical applications?). cirrus pro ducts are not designed, authorized or warranted for use in aircraft systems, military applications, products surgically implanted into the body, automotive safety or security de- vices, life support products or other cri tical applications. inclusio n of cirrus products in su ch applications is under- stood to be fully at the customer's ri sk and cirrus disclaims and makes no wa rranty, express, st atutory or implied, including the implied warranties of mer chantability and fitness for particular pu rpose, with regard to any cirrus product that is used in such a manner. if the cus tomer or customer's customer uses or permits the use of cirrus products in critical applications, customer agrees, by such use, to fully indemnify cirrus, its officers, di rectors, empl oyees, distributors and other agents from any and all liability, including attorneys' fees and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are tradem arks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners.

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